ASIC Design Efficiency Engineer - New College Grad 2025
at Nvidia
📍 Santa Clara, United States
$92,000-178,200 per year
SCRAPED
Used Tools & Technologies
Not specified
Required Skills & Competences ?
Python @ 3 Perl @ 3Details
We are now looking for an ASIC Design Efficiency Engineer. NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
Responsibilities
- Develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency.
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
- Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
Requirements
- Pursuing Bachelor’s or Master’s Degree in EE or CE (or equivalent experience).
- Proficiency in SystemVerilog or similar HDL.
- You have a solid understanding of logic design and computer architecture.
- Strong interpersonal skills are required along with the ability to work in a diverse product-oriented team.
Ways to stand out from the crowd:
- Pipeline processor or deep learning accelerator design/architecture experience.
- Low power or physical (synthesis/VLSI) design experience.
- Scripting knowledge in Python/Perl.
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!