Lead Performance Modeling Architect, CPU Fabric and LLC

Details

We are seeking a Lead Performance Modeling Engineer to guide our performance architecture team. You will act as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects. These models will scale from Automotive to Data Center platforms. You will guide a group of top-performing engineers, converting high-level product requirements into actionable architectural specifications and ensuring our silicon delivers industry-leading performance-per-watt. As a technical lead, you will balance individual technical contributions with team mentorship and multi-functional strategy.

Responsibilities

• Define the long-term vision for the modeling infrastructure, choosing between cycle-accurate, analytical, and stochastic modeling approaches to meet project goals.
• Lead a team of modeling engineers, providing technical mentorship, conducting code and architecture reviews, and promoting a culture of rigorous data-driven decision-making.
• Serve as the primary liaison between Architecture, RTL build, and Software teams to resolve complex performance bottlenecks and trade-offs.
• Drive adoption of advanced modeling methodologies (for example, hybrid emulation/simulation and AI-based performance optimization) to accelerate the build cycle.
• Allocate simulation workloads and engineering effort across multiple simultaneous projects in the automotive and data center sectors.

Requirements

• Master’s or Ph.D. in Computer Engineering or a related field (or equivalent experience).
• 8+ years of experience in high-performance silicon architecture and performance modeling.
• Extensive experience managing technical teams or complex projects in performance modeling or computer architecture.
• Proficiency in cache coherency protocols (examples: AMBA CHI, MESI), memory sub-systems, and high-speed interconnect fabric design.
• Significant experience building and architecting large-scale simulators in C++ or SystemC, with emphasis on modularity and simulation speed.
• Experience using statistical analysis to validate model accuracy against RTL or silicon and the ability to communicate complex performance cliffs to executive stakeholders.

Ways to stand out

• Full-stack performance experience: involvement from whiteboard sketches and C++ models through RTL integration and post-silicon performance tuning.
• Standardization influence: active participation in industry bodies (for example, CXL Consortium, Arm ecosystem committees) or a history of published architectural research.
• Scalability expertise: proven success addressing low-latency, safety-critical clusters and large, high-bandwidth mesh networks for cloud-scale deployments.
• Strong critical thinking: ability to explain how architectural decisions affect total cost of ownership for data centers or safety margins for automotive platforms.

Compensation & Benefits

• Base salary ranges (location- and level-dependent):
  • Level 4: 184,000 USD - 287,500 USD
  • Level 5: 224,000 USD - 356,500 USD
• Eligible for equity and company benefits.

Additional Information

• Applications accepted at least until May 10, 2026.
• Employer uses AI tools in recruiting processes.
• Employer statement: committed to fostering a diverse work environment and an equal opportunity employer.