Power Architecture and Optimization Engineer – New College Grad 2024

at Nvidia

📍 Santa Clara, United States

$92,000-178,200 per year

JUNIOR
✅ On-site

SCRAPED

Used Tools & Technologies

Not specified

Required Skills & Competences ?

Python @ 6 Networking @ 3 Perl @ 6

Details

We are now looking for a Power Architecture and Optimization Engineer – New College Grad! NVIDIA prides itself on having energy efficient products. We believe that maintaining our products' energy efficiency compared to the competition is key to our continued success.

Our team is privileged to work on Power Optimization of Data center, gaming and automotive GPU chips. We also work on power optimization of Networking chips. The gamut of GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Networking products. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, allowing us to influence architectural, design, and power management improvements.

Responsibilities

  • Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools to help improve product power efficiency.
  • Develop and share best practices for performing pre-silicon power analysis.
  • Perform comparative power analysis to spot trends and anomalies that warrant more scrutiny.
  • Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
  • Select and run a wide variety of workloads for power analysis.
  • Prototype a new architectural feature in Verilog and analyze power.

Requirements

  • Pursuing BS or MS in Electrical Engineering, Computer Engineering, or related fields.
  • Strong understanding of concepts of energy consumption, estimation, data movement, and low power design.
  • Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect). Previous internships and/or work on Power Optimization would be beneficial.
  • Strong coding/automation skills, preferably in Python, Perl, and C++.
  • Strong analytical skills with a go-getter attitude.

Benefits

  • The base salary range is 92,000 USD - 178,250 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
  • You will also be eligible for equity and benefits.