Senior Software R&D Engineer, Digital Logic Synthesis

Details

NVIDIA's success builds on a foundation of industry leading hardware. A key strategy in achieving this is our combining of the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++. We are seeking an innovative EDA Software R&D Engineer with particular interest in strategies and algorithms for RTL synthesis, digital logic, timing, and power optimization. Such optimization usually includes a mix of graph-based algorithms, AI, and feedback from RTL and physical designers. A solid understanding of DFT, clock distribution, power gating, and other SoC integration aspects is essential.

Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. Developers enjoy unusually high intellectual freedom and the ability to explore broad roles. The team owns the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Responsibilities

• Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
• Build physical-aware synthesis techniques using placement, congestion, and timing feedback to improve PPA (power, performance, area).
• Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
• Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions and integrate successful approaches into production.
• Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis.
• Write production-quality code and drive the roadmap, working across technical areas and with design teams to facilitate deployment.

Requirements

• MS or PhD in Electrical Engineering or Computer Science or equivalent experience.
• 6+ years experience in EDA software and/or VLSI flows, with significant work in logic synthesis or digital optimization.
• Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling/performance optimization, data structures, algorithms, testing).
• Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
• Expertise in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers.
• Good communication and interpersonal skills.

Ways to stand out from the crowd

• Previous work experience involving RTL logic synthesis and multi-stage logic optimization.
• Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization.
• Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use.
• Experience with various machine learning techniques.

Benefits & Additional details

• Base salary range: 168,000 USD - 264,500 USD (determined based on location, experience, and pay of employees in similar positions).
• Eligible for equity and benefits.
• Employment type: Full time.
• Location: Santa Clara, California, United States. #LI-Hybrid
• Applications accepted at least until March 13, 2026.
• NVIDIA uses AI tools in its recruiting processes and is an equal opportunity employer.