Senior System Verification Engineer

Details

NVIDIA is looking for a Senior System Verification Engineer to join our Emulation division. We are a worldwide recognized division noted for groundbreaking technology. We are work-flex, family and diverse team! NVIDIA invention of the GPU in 1999 accelerated the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new adventurous opportunities, that only we can seek, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Join us today!

Responsibilities

• Support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches).
• Bring up GPUs, SOCs, Switch, NIC on emulation, root causing system level test fails and emulator environment issues.
• Bring-up and verify High Speed protocols like PCIe/CXL/NVLINK/IB/Ethernet etc.
• Bring-up and verify Low speed protocols like I2C/I3C/SPI/UART.
• Bring-up/debug issues related to CPU and GPU Coherency.
• Collaborate continually with Design, DV, Power, Silicon Validation, Performance, and Software teams.
• Lead emulation vendors to debug issues using various tools.
• Write monitors and checkers that aid debug in hardware test issues and firmware/software bring-up.

Requirements

• M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field.
• 8+ years of proven experience.
• Proficient in Verilog and/or VHDL, C/C++ and SystemVerilog.
• Must have protocol knowledge of at least one of the High-speed interfaces: PCIe/CXL/NVLINK/IB/Ethernet etc.
• Good to have knowledge of low-speed protocols like I2C/I3C/SPI/UART and BMC interaction in server platforms.
• Working knowledge of CPU-GPU coherency.
• Experience with UVM verification environments and scripting with Perl, Python, and C/C++.
• Familiarity with hierarchical design approach, top-down design, SoC and system level verification.
• Work location onsite at Santa Clara, CA.

Benefits

• Eligible for equity and other benefits.
• Supportive of a diverse work environment and equal opportunity employer.