Silicon Validation Engineer

Details

NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team has an end-to-end view of the product development cycle—from early architecture definition through bringup to product release.

Responsibilities

• Develop new end-to-end methodologies, processes, and workflows targeting system-level silicon stress, concurrency, and PVT coverage.
• Lead debug efforts from the hardware side to root cause feature sequence bugs, silicon bugs, and system-level issues caused by interactions between multiple hardware and software features.
• Bring up new flows, tests, and PVT solutions.
• Apply insights from bring-up execution and post-action reviews to continually improve coverage.

Requirements

• BS or MS degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of experience in developing end-to-end silicon validation and stress testing, PVT methodologies for next-generation silicon.
• Deep understanding of GPU/System-on-Chip (SOC) system-level architecture.
• Experience with silicon active and low power features, boot, binning, PVT sensitivity, platform component losses.
• Post silicon debug and evaluation of fix options against product needs.
• Effective collaboration and communication across different functional teams.

Benefits

Competitive salaries and a generous benefits package. Eligible for equity and benefits. NVIDIA promotes a diverse work environment and is an equal opportunity employer.