Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026

Details

NVIDIA's success builds on a foundation of industry leading hardware. A key strategy in achieving this is our combining of the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++. We are seeking an innovative EDA Software R&D Engineer with particular interest in strategies and algorithms for RTL synthesis, digital logic, timing, and power optimization. Such optimization usually includes a mix of graph-based algorithms, AI, and feedback from RTL and physical designers, so having experience relevant to each of those areas would be ideal. In practice, techniques often depend on many related domains, so a solid understanding of DFT, clock distribution, power gating, and other SoC integration aspects is essential.

Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it!

Responsibilities

• Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
• Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA (power, performance, area).
• Develop strategies for rapidly analyzing RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
• Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
• Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
• Own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

Requirements

• MS or PhD in Electrical Engineering or Computer Science (or equivalent experience).
• Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization.
• Strong computer science fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing).
• Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
• Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers.

Ways to stand out

• Previous experience involving RTL logic synthesis and multi-stage logic optimization.
• Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization.
• Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use.
• Experience with various machine learning techniques.

Compensation & other details

• Base salary ranges: Level 2: 116,000 USD - 189,750 USD; Level 3: 136,000 USD - 218,500 USD (actual base depends on location, experience, and similar employees).
• You will also be eligible for equity and benefits.
• Applications for this job will be accepted at least until May 19, 2026.
• NVIDIA uses AI tools in its recruiting processes and is an equal opportunity employer committed to diversity and inclusion.