Senior ASIC Design Engineer

Details

As a member of our digital logic interconnect design team, you will be responsible for implementing logic for our next-generation GPUs and SOCs which enable high-performance interconnect of multi-GPU/CPU/DPU system topologies for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment solutions. Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization, and verification support. The ideal candidate will have 10+ years of direct experience with PCIE Physical/ Data-Link Layer or other industry standard protocols like CXL, AXI, CHI, UCIe USB, SATA.

Responsibilities

• Micro architecting the next generation of PCIE PL and DL.
• Implementing readable, high-performance, area and power-efficient RTL to achieve design targets, including upcoming performance, adaptability, and safety industry standards.
• Collaborating with architects, external partners, software engineers, and circuit designers to deliver best in class IP.
• Partnering with our Physical Design team on partitioning, floorplanning, and timing closure.
• Providing design documentation, triaging and debugging functional and performance bugs, integration and infrastructure support and development.

Requirements

• Bachelors Degree in EE, CS or CE or equivalent experience.
• 8+ years of relevant experience or an Advanced Degree with equivalent experience.
• 5+ years experience in coding PCIE PL/DL logic or lower layers of the OSI stack in general.
• In-depth understanding of physical design.
• Strong working knowledge of Verilog or System Verilog.
• Strong collaboration and communication skills.
• Able to lead junior engineers and assist management with task assignments, scheduling, and other project management tasks.

Ways to stand out from the crowd:

• Good knowledge of PCIe PL/DL sub blocks such as: data scrambling, packet framing, NRZ/PAM4 encoding, equalization, TLPs/DLLPs, LTSSM, power states, errors, etc.
• Knowledge of alternate protocol negotiation, CXL/UCIe would be an added advantage.
• Experience in handling post-silicon bringup, and good understanding of signal integrity concepts.
• Understanding of firmware/driver structures and their interaction with HW.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come join our design team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.