Senior VLSI CAD Engineer, ECO Tools - New College Grad 2025
SCRAPED
Used Tools & Technologies
Not specified
Required Skills & Competences ?
Python @ 4 R @ 4 Algorithms @ 4 Perl @ 4 API @ 4Details
NVIDIA's continued advancement of world-leading hardware requires a combination of the best of both external and internal EDA tools. Their team develops and deploys highly optimized internal tools used across all NVIDIA product lines many thousands of times per day. The role is for a CAD R&D Engineer excited to innovate in algorithms related to ECO automation, including mapping, patch size minimization, reconfiguration of clocks, power, and DFT, as well as incremental timing and power optimization. A thorough understanding of both VLSI hardware design and efficient software implementations is key. Experience with GUIs is also a plus. ECOs involve nearly every area of the VLSI flow, making this a broad and highly visible role.
Developing software within a leading hardware company enables focus on the latest processes and most advanced designs without legacy support burdens. Developers enjoy intellectual freedom and a chance to work across many technical areas, seeing successes realized in top AI hardware.
Responsibilities
- Innovate across the entire VLSI flow to make incremental recovery and optimization fast and seamless, primarily involving C++. Improve or replace in-house algorithms for incremental CTS, scan insertion, power hookup, placement, timing optimization, etc.
- Educate RTL teams on best practices identified and advanced.
- Help develop GUIs for design visualization and other tools to boost designer productivity.
- Potential expansion into other physical design implementation and analysis tools.
- Own the full process from discovery and invention of new optimization opportunities to solution development and deployment within design teams.
Requirements
- Recent graduate with MS or PhD in Electrical Engineering or related field, or equivalent experience.
- Experience across VLSI, including synthesis, clocks, DFT, power distribution, timing, place & route.
- Proficiency in C++.
- Familiarity with SAT solvers and logic minimization packages.
- Interest in enhancing design team efficiency with intuitive GUIs and APIs.
Ways to Stand Out
- Prior physical design experience.
- Experience with GUI frameworks such as ImGui or Qt.
- Background in synthesis and timing tools like Design Compiler, Fusion Compiler, and PrimeTime.
- Experience using AI-coding assistants such as Cursor.
- Background with scripting languages like Python, Perl, or Tcl.
Benefits
- Competitive base salary range from $108,000 to $212,750 USD depending on location, experience, and market comparisons.
- Equity and benefits eligibility.
- Commitment to diversity and equal opportunity employment.