Network Engineer - ML Infrastructure (High-Speed Interconnects)

Details

SpaceXAI is building large-scale AI training and inference infrastructure using advanced compute and switching hardware. This hands-on role focuses on designing, building, and optimizing high-bandwidth, low-latency, power-efficient network fabrics for AI/ML clusters. The engineer will work across interconnects connecting GPUs and switches within and between data centers, owning projects from design and development through deployment and operations.

The role focuses on the physical layer and system-level integration of copper interconnects, including ACC, AEC, and CPC, and optical interconnects, including FRO, LRO/TRO, LPO, AOC, and CPO. The work involves 200G+ SerDes, PAM4, photonics, signal integrity, diagnostics, and large-scale AI systems.

Responsibilities

• Design, validate, and productize high-speed copper and optical connectivity solutions for AI clusters at 100,000+ GPU scale.
• Own vendor due diligence and onboarding for new 1.6T products, including AECs and pluggable optical transceivers such as DR4/8 and FR4, with rigorous bring-up and characterization.
• Investigate the use of LPO and LRO in the network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Perform pathfinding for new interconnect modalities, including VCSEL, microLED, and THz radio-based solutions, to improve network economics and reliability.
• Work with transceiver, cable, SerDes, DSP, and silicon photonics foundry vendors to influence roadmaps and ensure timely delivery of next-generation solutions.
• Collaborate with ML training teams to translate workload communication patterns into interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root-cause investigations, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation, and automated qualification pipelines.
• Stay current with industry standards, including OIF CMIS and IEEE, and emerging technologies such as multi-core and hollow-core fiber, 448G SerDes, TFLN, and ring resonators.
• Define and improve team processes and contribute to scaling and maintenance efforts.

Requirements

• At least 8 years of hands-on experience designing, deploying, and operating high-speed copper and optical interconnects, preferably in a module design role or hyperscale data center environment.
• Master's or PhD degree in Electrical Engineering, Photonics, or Physics.
• Deep knowledge of PAM4 SerDes performance, equalization, jitter, and crosstalk.
• Solid operational understanding of FEC, retimers, TIAs, and drivers.
• Deep knowledge of optical link budget analysis and performance metrics, including TDECQ, OMA, Tcode, stressed receiver sensitivity, and associated diagnostics.
• Expertise in transceiver components, including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes, and characterization.
• Knowledge of thermal, mechanical, power, and signal-integrity constraints in dense hardware.
• Knowledge of SiPh design processes, yield improvement, and reliability testing.
• Familiarity with CPO technologies and their challenges and risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs, and CMs.
• Strong problem-solving skills and the ability to thrive in a fast-paced, ambiguous setting.
• Strong communication skills and the ability to concisely and accurately share knowledge with teammates.

Compensation And Benefits

• Base salary: $180,000–$440,000 USD per year.
• Equity.
• Comprehensive medical, vision, and dental coverage.
• Access to a 401(k) retirement plan.
• Short- and long-term disability insurance.
• Life insurance, discounts, and other perks.