Principal Deep Learning Communication Architect

at Nvidia

USD 272,000-431,200 per year

SENIOR

✅ On-site

Tech Stack
Tag name is followed by "@" symbol and proficiency level value. About proficiency levels:

1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;

3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;

7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;

10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.

AI @ 6 Agentic AI @ 6 Algorithms CUDA @ 4 Communication @ 1 Deep Learning @ 8 GPU @ 4 HPC @ 8 InfiniBand @ 4 JAX @ 1 LLM @ 7 MPI @ 6 NCCL @ 6 NVLink Networking @ 6 PyTorch SGLang @ 7 Technical Proficiency @ 6 TensorRT @ 7 vLLM @ 7

Architecture Leadership: Define the long-term technical roadmap for communication libraries across NVIDIA’s next-generation platforms. You will ensure the seamless scaling of models to clusters comprising hundreds of thousands of nodes.
AI Communication Library Design: Lead the development of next-generation communication primitives and collective algorithms. This includes optimizing for heterogeneous interconnects such as NVLink, Spectrum-X (Ethernet), and Quantum-X (InfiniBand).
Application- Communication Library Co-Design: Partner with application developers to architect and implement specialized communication primitives. You will ensure that AI and HPC libraries—including NCCL, NIXL, NVSHMEM, UCC, and UCX—evolve to meet the requirements of trillion-parameter and Agentic AI.
Hardware/Software Co-Design: Collaborate with silicon Aarchitects and software engineers to influence hardware specifications for next-generation networking, ensuring they meet the evolving demands of trillion-parameter LLMs and Agentic AI.
Quantitative Modeling: Develop high-fidelity analytical models and simulators to predict system behavior under emerging workloads.

Ph.D. or M.S. in Computer Science, Electrical Engineering, or a related field (or equivalent experience), with 12+ years of industry experience in high-performance computing (HPC) or distributed deep learning.
Parallelism Expertise: Deep understanding of 3D parallelism (Data, Tensor, Pipeline) and advanced strategies including Context Parallelism, Expert Parallelism, and Zero Redundancy Optimizer (ZeRO) variants.
Technical Proficiency: Deep technical proficiency with NCCL, UCX, UCC, NVSHMEM, or MPI. Experience with RDMA, RoCE, and low-level InfiniBand verbs is required.
Inference & Serving: Advanced knowledge of high-throughput inference engines and schedulers, specifically TensorRT-LLM, vLLM, SGLang, and NVIDIA Dynamo.
GPU Architecture: Expert knowledge of the NVIDIA GPU memory hierarchy (HBM3e/HBM4, L2 cache) and CUDA programming models.

Framework Development: Hands-on experience developing within Megatron-Core, DeepSpeed, or JAX/XLA, with an understanding of how these frameworks interact with low-level communication runtimes is a plus.
Significant upstream contributions to major open-source projects (e.g., PyTorch Distributed, KServe, or Ray).
A proven track record of deploying and optimizing models on NVIDIA platforms or similar rack-scale systems.
A strong portfolio of patents or papers in top-tier systems/architecture venues (e.g., ISCA, ASPLOS, NeurIPS, SC).