Senior Verification Engineer

Details

NVIDIA is seeking a skilled Senior Verification Engineer to join its Display Team and help verify GPU and SoC display engines. Working alongside architects and ASIC engineers, this role owns test plan development, verification sign-off, and infrastructure for high-quality display IPs used across consumer, professional, automotive, and AI markets.

Responsibilities

• Define verification scope, develop and drive functional and performance test plans, and build scalable UVM-based infrastructure.
• Leverage agentic AI to automate repetitive tasks, accelerate debugging, and improve team efficiency.
• Develop UVM testbenches and checkers.
• Work with C/C++-based testbenches and debug reference models and designs developed in HLS.
• Track verification metrics and drive coverage closure.
• Analyze architectural solutions and collaborate with architects to develop silicon-proven designs.
• Collaborate across NVIDIA sites globally and work with external partners and customers to deploy verification flows.
• Ensure consistent display IP behavior across diverse tool stacks.
• Debug complex integration issues across organizational boundaries.

Requirements

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
• 10+ years of relevant experience.
• Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++.
• Experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches, ideally on shipped silicon.
• Proficiency with industry EDA tools including VCS, Verdi/Debussy, and GDB.
• Strong software engineering practices, including writing clean and maintainable code, version control, and code review.
• Domain knowledge of display pipelines and protocols, including DisplayPort, HDMI, and MIPI DSI/CSI.
• Understanding of MMU interaction with ISO clients and system low-power features such as clock gating, power domains, retention, and entry/exit sequences.
• Ability to independently investigate unfamiliar sub-blocks, communicate clearly across time zones and organizational boundaries, and use agentic AI to solve engineering challenges.

Preferred Qualifications

• Prior Display Unit Verification experience.
• Familiarity with pixel processing, ISO performance testing, and HLS-based designs.
• Hands-on experience verifying display protocols end-to-end, MMU/SMMU behavior under ISO traffic, and system-level low-power sequences.
• Experience shaping architectural specifications and micro-architecture decisions.

Benefits

• Equity and benefits are provided.
• NVIDIA is committed to fostering an inclusive work environment and is an equal opportunity employer.
• Applications will be accepted at least until July 27, 2026.