ML Silicon Performance Lead

Details

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for advanced AI workloads. The team is developing future generations of AI-native silicon and tightly integrated systems to power OpenAI’s supercomputing platform by co-designing chips, systems, tools, and methodologies.

The role drives hardware/software co-design for silicon architecture, connecting model and workload requirements with compute, memory, and specialized acceleration capabilities. The work spans models, kernels, compilers, and silicon to maximize performance, efficiency, and scalability across current and future generations of AI silicon.

Responsibilities

• Drive hardware/software co-design across ML research, compiler, and silicon teams, shaping kernel implementations and hardware capabilities to meet workload performance and efficiency goals.
• Translate model and workload needs into kernel performance targets and compute, memory capacity, and bandwidth requirements.
• Map and optimize ML kernels for the architecture using insights from data movement, memory hierarchy, and execution efficiency.
• Co-design support for new data structures and quantization formats across kernels, compilers, and silicon, balancing model quality, numerical behavior, performance, power, and implementation cost.
• Define and help develop specialized acceleration IP, determining the appropriate division of functionality across software, instructions, and dedicated hardware.
• Drive ML performance modeling and simulation with the compiler team to compare hardware/software design options, expose bottlenecks, and quantify end-to-end benefits on representative workloads.
• Partner with the Silicon Architecture lead and silicon team to specify and validate new IP, using kernel and simulation results to refine requirements and prioritize architectural improvements.

Requirements

• Deep experience with ML accelerator architecture, including compute resources, memory systems, and data movement.
• Ability to translate model-level behavior into concrete kernel requirements and hardware design decisions.
• Experience building or using accelerator performance models and simulators, validating their assumptions, and interpreting their limitations.
• Hands-on experience optimizing ML kernels, identifying bottlenecks, and improving utilization, locality, and execution efficiency.
• Understanding of quantization and numerical formats, including their effects on model quality, memory bandwidth, compute efficiency, and hardware support.
• Experience with hardware/software co-design and evaluating whether capabilities belong in a kernel, compiler, instruction set, or dedicated hardware.
• Ability to work effectively across research, compiler, and silicon teams and build alignment through technical evidence.
• Candidates may need to meet certain legal status requirements under U.S. export control laws and regulations.

Benefits

• Base pay of $287,000–$485,000 per year, plus equity, performance-related bonuses for eligible employees, and benefits.
• Medical, dental, and vision insurance, with employer contributions to Health Savings Accounts.
• Pre-tax FSA, dependent care FSA, and commuter accounts.
• 401(k) retirement plan with employer match.
• Paid parental, medical, and caregiver leave.
• Paid time off, company holidays, office closures, and paid sick or safe time as required by law.
• Mental health and wellness support.
• Employer-paid basic life and disability coverage.
• Annual learning and development stipend.
• Daily office meals and eligible meal delivery credits.
• Relocation support for eligible employees.
• Additional benefits may include charitable donation matching and wellness stipends.