Senior Manufacturing and System Co-Design Workflow Engineer

Details

Build the infrastructure that keeps every NVIDIA chip aligned from first specification to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss.

The role leads the methodology and infrastructure that maintains holistic, systematic alignment at scale across the full portfolio. The strongest candidates design the workflow before being asked to fix a program and build the checks and automation that confirm alignment holds long after they have moved on to the next problem.

Responsibilities

• Define manufacturing specification types, including schema and semantics, derived from system PORs and features.
• Own the methodology governing how specification work is structured, versioned, and validated across the program lifecycle.
• Develop production-grade Python pipelines and automated checks that detect specification drift between system POR and manufacturing test programs, including ATE, SLT, BLT, and L10+.
• Integrate SMAC work into the end-to-end program spine, milestones, gates, and artifacts.
• Define explicit TPM-driven attestation when checks lag.
• Integrate tooling into an agent-ready harness, including CLIs, MCPs, bug and specification retrieval, human-in-the-loop checkpoints, and evaluation-based CI gates running against real silicon workflows.
• Drive adoption of SMAC methodology and tooling across Post Silicon (Prod), Operations, and DFX (DFT/DFP) teams.
• Build infrastructure that supports alignment across GPU, SoC, and CPU programs and generations.

Requirements

• Bachelor's degree, master's degree, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or Systems Engineering.
• 8+ years of experience in system software, silicon bring-up, or productization engineering.
• Strong Python and systems skills.
• Experience shipping production services and data pipelines.
• Deep understanding of the specification ecosystem, including system POR, guard-bands, manufacturing screen specifications, and test insertion constraints.
• Proven track record of cross-organizational influence, including methodologies and workflows adopted by other teams.
• Ability to interpret silicon and productization outputs such as speed, power, and binning.
• Ability to apply AI with sound judgment, including producing reviewable artifacts and identifying where manual validation remains required.

Preferred Qualifications

• Experience establishing a cross-organizational workflow from scratch.
• Experience shipping automation that achieves adoption across resistant partner teams.
• Experience building LLM-backed tools used by subject matter experts.
• A workflow-architect mindset focused on optimizing stages, runtime, and toil across an entire system.

Compensation and Benefits

• Base salary range for Level 4: $168,000–$264,500 USD per year.
• Base salary range for Level 5: $196,000–$310,500 USD per year.
• Eligible for equity and benefits.
• Applications accepted at least until August 10, 2026.
• NVIDIA uses AI tools in its recruiting processes.
• NVIDIA is an equal opportunity employer.