Senior Multi-GPU Signal Processing and System Architecture Engineer
at Nvidia
USD 200,000-396,800 per year
Tech Stack
Tag name is followed by "@" symbol and proficiency level value.
About proficiency levels:
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
CUDA @ 6
GPU @ 6
HPC
NVLink @ 6
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
Details
We are seeking a self-motivated senior engineer for the Aerial Omniverse Digital Twin team. This hire will own the design and implementation of the real-time signal-processing subsystem that converts physics-based channel descriptions into received signals for large numbers of emulated devices, across systems of potentially thousands of interconnected GPUs! This position offers the opportunity to work on foundational technology for 5G and 6G network simulation, using NVIDIA's world-class compute and interconnect platforms!
Responsibilities
- As a member of NVIDIA's Aerial team, you will design and implement GPU kernels that apply time-varying, multi-antenna channels to OFDM signals under hard real-time deadlines.
- Architect the inter-cell data-flow layer—ensuring that the information each cell needs to model interference from its neighbours is compressed, transported, and consumed within the available NVLink and NIC budgets at scale.
- Work with the propagation engine and RAN stack teams to orchestrate the end-to-end simulation pipeline, ensuring that propagation updates, channel application, and stack execution remain synchronized across hundreds or thousands of GPUs.
- Assess design and implementation trade-offs between physical fidelity, latency, and system scalability.
Requirements
- PhD in high-performance computing, computer architecture, signal processing, or wireless communications (or equivalent experience).
- 12+ years of proven experience.
- Proficiency in CUDA kernel design with attention to memory hierarchy, register pressure, and HBM bandwidth planning, with a track record of writing production-quality GPU code that meets hard real-time deadlines.
- Demonstrated ability to build and reason about data flows across multi-device GPU systems (NVLink, NIC/RDMA) with explicit bandwidth and latency accounting.
- Working knowledge of OFDM signal processing and the 5G NR physical layer, sufficient to implement and validate a channel-emulation pipeline.
- Impactful publications involving GPU-accelerated numerical workloads or real-time system design.
Benefits
- You will also be eligible for equity and benefits.
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