Tech Stack
Tag name is followed by "@" symbol and proficiency level value.
About proficiency levels:
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
AI @ 4
Communication @ 7
HPC
Leadership @ 7
Machine Learning
Networking @ 4
Scoping @ 4
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
Details
Anthropic is building custom silicon for Claude and is seeking a Technical Program Manager to own end-to-end execution of the silicon program, from architecture definition through tapeout, first-silicon bring-up, and production ramp. The role works with domain experts across front-end design, verification, physical design, DFT, analog/mixed-signal, foundry, and packaging, while establishing the execution processes for the program.
Responsibilities
- Own the integrated silicon program plan, including architecture closure, RTL freeze, design verification milestones, IP delivery, physical-design closure, DFT, tapeout, and post-silicon bring-up.
- Drive execution across external ASIC design partners, IP vendors, foundries, and packaging and test providers.
- Run technology and IP selection programs, track candidate vendors and options, drive evaluations, and support build, buy, and license decisions with engineering leadership.
- Build lightweight execution mechanisms, including milestone definitions, risk and dependency tracking, design reviews, release management, and executive reporting.
- Manage interfaces between silicon and hardware systems teams responsible for package, board, and bring-up activities.
- Coordinate with inference, kernel, and compiler teams on hardware-software co-design.
- Own post-silicon activities, including bring-up planning, ATE/test handoff, sample distribution, validation, and production-readiness planning.
- Develop and share AI-assisted program-management approaches for schedule and dependency modeling, specification and milestone consistency checking, partner-deliverable tracking, and status synthesis.
Requirements
- At least 8 years of experience in silicon or SoC program management, chip leadership, or an equivalent role owning a chip schedule end to end.
- Direct ownership of at least one program that taped out and reached production, including detailed understanding of milestones, schedule slips, and corrective actions.
- Technical fluency across the silicon lifecycle, including front-end design, design verification, physical design, DFT, foundry operations, and packaging.
- Experience managing external silicon partners such as ASIC houses, IP vendors, foundries, or OSAT providers, including statement-of-work scoping, delivery tracking, and escalation.
- Experience creating program mechanisms from scratch for ambiguous, fast-moving efforts.
- Strong written communication skills for plans, reviews, and executive updates.
- Ability to operate autonomously with limited process on a highly dynamic program.
- Minimum education of a bachelor's degree or equivalent combination of education, training, and experience. Relevant fields include electrical engineering, computer engineering, computer science, or related disciplines.
Preferred Qualifications
- Experience with ML accelerators, high-performance computing, networking, or other large, high-bandwidth SoCs at advanced process nodes.
- Experience with first-generation or early silicon programs, including establishing flows, methodology, or vendor relationships.
- Experience with both partner-executed and fully in-house programs.
- Prior hands-on engineering experience in design, design verification, physical design, DFT, or signal integrity/power integrity.
- Familiarity with the chip-package-system interface and co-design with hardware systems teams.
- Experience with hardware-software co-design programs involving compiler, kernel, or runtime teams.
- Practical experience using AI tools in a professional workflow.
- BS/MS in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.
Benefits
Anthropic offers competitive compensation and benefits, optional equity donation matching, generous vacation and parental leave, flexible working hours, and office space for collaboration. Staff are currently expected to work from one of the company's offices at least 25% of the time, although some roles may require more office time.