Research Engineer, Chip Design RL (Reinforcement Learning)
at Anthropic
USD 500,000-850,000 per year
Tech Stack
Tag name is followed by "@" symbol and proficiency level value.
About proficiency levels:
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
AI @ 3
HPC
Machine Learning
Reinforcement Learning @ 3
- 1-2 — basic awareness. Minimal hands-on experience, and a rudimentary understanding of the technology's purpose;
- 3-6 — daily use. Comfortable and regular usage, capable of handling common tasks and challenges related to the technology;
- 7-9 — you are an expert, you can teach others, you know all the pitfalls and tricks;
- 10 — exceptional knowledge, comprehensive understanding, and adeptness in all aspects of the technology, including advanced problem-solving. Think twice before claiming or demanding such level.
Details
Anthropic is hiring a Research Engineer for the Code RL team within its Reinforcement Learning organization. The role focuses on advancing AI models' ability to design silicon by converting chip design expertise into tasks and learning signals for models.
Responsibilities
- Invent, design, and implement reinforcement learning environments and evaluations for agentic RTL generation, design verification—including formal verification—and physical design optimization.
- Address cross-cutting reinforcement learning challenges, including EDA-tool latency optimization and proxy rewards.
- Conduct experiments and help shape the research roadmap.
- Deliver research into research and production training runs.
- Collaborate with researchers and engineers across and outside Anthropic.
Requirements
- Expertise in ASIC or FPGA design, including RTL, design verification, UVM, formal methods, coverage-driven verification, physical design, synthesis, place-and-route, timing closure, PPA optimization, DFT, and ECOs.
- Fluency with industry EDA tools and processes.
- Experience taping out chips and taking designs from specification to silicon.
- Ability to balance research exploration with engineering implementation.
- Passion for AI's potential and commitment to developing safe and beneficial systems.
- A bachelor's degree or equivalent combination of education, training, and experience.
- A field of study relevant to the role, as demonstrated through coursework, training, or professional experience.
Strong candidates may also have:
- Experience with reinforcement learning, evaluations, or environments.
- Experience building tooling or automation around chip design flows.
- Experience with ML accelerators or high-performance computing hardware.
- Familiarity with high-level synthesis or architecture simulators.
Compensation
- Annual salary: $500,000–$850,000 USD
Work Policy and Logistics
- Locations: San Francisco, California, or New York City, New York.
- Anthropic currently expects staff to work from one of its offices at least 25% of the time, although some roles may require more office time.
- Anthropic sponsors visas and makes reasonable efforts to obtain visas for candidates who receive an offer, with assistance from an immigration lawyer.
- Benefits include competitive compensation, optional equity donation matching, generous vacation and parental leave, flexible working hours, and office collaboration space.
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